8-bit serial to parallel converter in vhdl

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Sweta25 Junior Member level 1. Hello Everyone, I am working on some codes for the serial-to-parallel converter I wrote some codes but I am encountering some errors I would highly appreciate some help Code VHDL - [ expand ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 PFA : serial - to - parallel converter library IEEE ; use IEEE.

Last edited by a moderator: Dec 10, FvM Super Moderator Staff member. The error is in line 25, as reported in the error message. Just delete the i. FvM said:. Click to expand Last edited: Dec 10, Hello, I rewrote the codes for the Serial to Parallel and problem is that I need 7 8-bit parallel outputs but on stimulating I am getting only 1 8-bit parallel output..

Thanks my codes Code:. You are writing your code like a software program. VHDL is a hardware description language.

For loops are not use to iterate over a block of code like you are doing. For loops are used to generate repeated copies of something e. Forget everything you know about C when writing HDL.

Viewed 12k times. I have a question which is probably in 2 parts: I am using a nominally 32 bit integer variable which I would like to write to an 8 bit UART as 4 bytes i. Martin Irvine Martin Irvine 1 1 gold badge 2 2 silver badges 8 8 bronze badges.

Add a comment. Active Oldest Votes. You seem to be on the right track. I believe there are two basic solutions to this problem: Register the output value as a bit vector, and use different ranges for each output operation as you did in your code example Register the output value as a bit vector, and shift this value 8 bits at a time after each output operation.

This way you can use the same range in all operations. Sign up or log in Sign up using Google. Sign up using Facebook. Sign up using Email and Password. Post as a guest Name. We will see how to implement the VHDL code for a serial to parallel interface in order to get back the parallel data bus we sent in the transmitter device. Let assume the parallel data bus of the Serial to Parallel converter to be N bit.

The parallel output to the module will be available every N clock cycle since N clock cycles are needed to load the shift register that provided the parallel output as in Figure2. With respect to the parallel to serial converter in this case no error detection logic is present. The output parallel data rate is slower than the input serial data rate, so no error condition can occur.

In the simulation of all the figures below, the clock is set to 10 ns, so 80 ns mean 8 clock cycles. In order to realize the test bench, the parallel to serial converter of this post is used. As a convention , the first serial output bit is the MSB of the input parallel data.